The present invention relates to integrated circuit design methodologies, and more specifically, to a methodology that evaluates timing performance parameter sensitivities to manufacturing variations of each of the elements within a path to identify how much each element will increase or decrease the timing performance parameter of the path for each change in each manufacturing variable associated with manufacturing the elements.
Manufacturing process variation is increasing as geometries reduce in size. Statistical Static Timing Analysis can model variations and account for it in timing tests. Reducing variation through early design changes can improve design robustness.